1. Field of the Invention
The present invention relates to a pixel structure, and more particularly, to a pixel structure having thin film transistors with a parasitic capacitance compensation structure to improve display picture quality.
2. Description of the Prior Art
A conventional thin film transistor liquid crystal display device primarily includes a thin film transistor array substrate, a counter substrate and a liquid crystal layer sandwiched in between the two substrates. The thin film transistor array substrate primarily includes a plurality of scan lines, a plurality of data lines, a plurality of thin film transistors disposed between the scan lines and the data lines, and a pixel electrode disposed correspondingly to each of the thin film transistors. The counter substrate includes a common electrode. Each of the thin film transistor described above includes a gate electrode, a semiconductor layer, a source electrode and a drain electrode, serving as a switch unit for the liquid crystal display unit.
The manufacturing process of the thin film transistor array substrate typically includes multiple exposure, photolithography and etching steps. In a typical manufacturing process, the gate electrode and the scan line are formed by a first metal layer (Metal 1) whereas the source electrode, the drain electrode and the data line are formed by a second metal layer (Metal 2). Also, at least a dielectric layer is disposed between the Metal 1 and the Metal 2. In the structure of the thin film transistor, the gate electrode at least partially overlaps the drain electrode, therefore a gate-drain electrode parasitic capacitance (referred to as Cgd) often exists due to the overlapping of the gate electrode and the drain electrode.
As for the liquid crystal display devices, a Clc voltage transferred from the data line is applied to a liquid crystal capacitor Clc formed by the pixel electrode, the common electrode and the liquid crystal layer; and the Clc voltage has a particular relationship with respect to the light transmittance of liquid crystal molecules in the liquid crystal layer. Therefore, the predetermined images can be displayed on the display device via controlling the Clc voltage applied to the liquid crystal capacitor Clc in accordance with the display images. However, due to the presence of the gate-drain electrode parasitic capacitance Cgd, the Clc voltage maintained on the liquid crystal capacitor Clc varies with respect to a voltage variation of the scan line. Such Clc voltage variation is known as the feed-through voltage ΔVp, and can be represented by the equation (1) below:ΔVp=[Cgd/(Clc+Cgd+Cst)](Vgon−Vgoff)  (1)
wherein Vgon−Vgoff represents the voltage variation of the scan line, and Cst stands for the storage capacitor.
During the thin film transistor manufacturing process, misalignments induced by machine variance cause variation in the overlapping area between the gate electrode and the drain electrode for each thin film transistor, accordingly resulting in gate-drain parasitic capacitance Cgd variations. As a result, pixels would have different feed-through voltages AVp, causing display picture quality degradation such as flickering.
In order to overcome the negative impacts induced by the gate-drain electrode parasitic capacitance Cgd variation, U.S. Pat. No. 5,097,297, Chinese Patent Publication Number 101359692 and Chinese Patent Number 201000520 provide some different pixel structure designs respectively. The technology provided by these patents is useful to solve parasitic capacitance Cgd variation, however, in some particular cases, there are some particular thin film transistor designs that the aforementioned references may not be suitable to solve such particular technical problems. Therefore, the negative impacts on the displaying picture quality induced by the gate-drain electrode parasitic capacitance Cgd variations remain to be resolved.